1. Field of the Invention
The present invention relates to a position detecting device and a position detecting method, and, particularly, to a position detecting device and a position detecting method effective with regard to wafer alignment in semiconductor exposure devices.
2. Description of the Related Art
Increasingly miniaturized and high-density circuits necessitate that semiconductor device manufacturing projection exposure apparatuses be able to project circuit patterns on reticles onto wafer surfaces for exposure at even higher resolution. The projection resolution of a circuit pattern depends on the apertures (NA) of the projection optical system and on the exposing light wavelength, so methods are being employed for raising the resolution, such as increasing the NA of the projection optical system or using light having a shorter wavelength for exposure. With regard to the latter, the exposure light source has made a transition from g rays to i rays, and from i rays to the excimer laser. Exposure devices using an excimer laser with an oscillation wavelength of 248 nm and 193 nm are already in practical use.
Currently, even shorter wavelength VUV exposure using a wavelength of 157 nm, and EUV exposure using a wavelength of around 13 nm, are being studied as candidates for next-generation exposure.
Also, there is an increasing variety in semiconductor device manufacturing processes, and CMP (Chemical Mechanical Polishing) processes and the like are being introduced as smoothing techniques to resolve the problem of insufficient depth of the exposure apparatus.
Also, there is a great variety of structures and materials for the semiconductor devices, with the P-HEMT (Pseudomorphic High Electron Mobility Transistor) and M-HEMT (Metamorphe-HEMT) made up of a combination of compounds, such as GaAs or InP, or the like, and HBT (Heterojunction Bipolar Transistor) using SiGe or SiGeC, or the like, for example, being proposed.
On the other hand, increased miniaturization of the circuit pattern means that highly-precise alignment between the reticle upon which the circuit pattern is formed and the wafer upon which the pattern is cast is accordingly necessary. The required precision is ⅓ of the circuit line width, so with a current design using 180 nm, for example, the required precision is 60 nm.
Alignment in an exposure apparatus is performed by exposure transferring of alignment marks on the wafer at the same time as the circuit pattern on the reticle, optically detecting the position of the alignment marks at the time of exposing the circuit pattern of the next reticle on the wafer, and positioning the wafer as to the reticle. Techniques for detecting the alignment include a method wherein the alignment marks are enlarged and taken with a microscope so as to detect the position of the mark image, a method wherein a diffraction grating is used as alignment marks so as to detect the phase of interference signals from interference with the diffraction light therefrom, thereby detecting the position of the diffraction grating, and so forth.
In the current situation of the semiconductor industry, as described above, improving the precision of overlaying on device wafers at the time of using exposure apparatuses is an issue, which is crucial in improving the capabilities of the semiconductor devices and improving production yield. However, the fact is that while circuit patterns can be configured well due to introduction of special semiconductor manufacturing techniques such as CMP processing and the like, but irregularities in alignment mark shape occur from one wafer to another or from one shot to another, resulting in non-symmetric alignment mark structures, frequently bringing about deterioration in the alignment precision.
The cause of non-symmetric alignment mark structures can be attributed to an increased difference between the line width of the circuit pattern and the line width of the alignment mark, due to increasingly miniaturized circuit patterns. The process conditions for film formation, etching, CMP, etc., are optimized for the line width of the circuit patterns (a line width of 0.1 to 0.15 μm), so structures with a line width in generally the same order do not become non-symmetric, but the alignment marks with a large line width in comparison with the circuit patterns (a line width of 0.6 to 4.0 μm) do not match the optimal process conditions, and accordingly, may turn out being non-symmetric. Attempting to match the line width of the alignment marks with the line width of the circuit patterns results in the signal intensity or contrast deteriorating due to insufficient resolution of the detection optical system used for alignment, leading to poorer stability in alignment signals. A detection optical system capable of detecting alignment marks with the same line width as the circuit patterns would require an alignment light source with a large NA and a short wavelength, which is a detection optical system on the same level as with the projection optical system, leading to a new problem of increased costs for the apparatus.
Currently, this issue is being dealt with by changing the process conditions by trial and error so as to be suitable for both the alignment marks and circuit patterns, or to make several types of alignment mark line widths for exposure evaluation, and use the alignment marks with the best line width.
Accordingly, this has required great amounts of time for determining optimal conditions (parameters). Also, even after parameters are determined, in the event that a process error, or the like, occurs, there is the need to change the parameters for the manufacturing apparatus accordingly, with the changes in the manufacturing process, which requires a great amount of time again. Moreover, even more miniaturized circuit patterns, new semiconductor processes, 300 mm wafers, and so forth, are expected to make manufacturing with no defects on the whole surface of a wafer in both the circuit patterns and alignment marks even more difficult.